Publications

  1. S. Zahedi, Q. Llull, B. Lee. "Amdahl's Law in the datacenter era: A market for fair processor allocation," Proc. 24th International Symposium on High-Performance Computer Architecture (HPCA), Vienna, Austria, February 2018.


  2. Q. Llull. "Microeconomic models for managing shared datacenters," Ph.D. Dissertation, Duke University, May 2017.
  3. Q. Llull, S. Fan, S.M. Zahedi, B. Lee. "Cooper: Task colocation with cooperative games," Proc. 23rd IEEE International Symposium on High-Performance Computer Architecture (HPCA). Austin, TX, February 2017.
  4. S. Fan, Q. Llull, B. Lee. "Predicting sensory data and extending battery life for wearable devices," Proc. 18th Workshop on Mobile Computing Systems and Applications (HotMobile). Sonoma, CA, February 2017.
  5. S. Zahedi, S. Fan, M. Faw, E. Cole, B.C. Lee. "Computational sprinting: Architecture, dynamics, and strategies," ACM Transactions on Computer Systems (TOCS), 34(4):12.1-12:26, January 2017.


  6. T. Lehman, A.D. Hilton, B.C. Lee. "PoisonIvy: Safe speculation for secure memory," Proc. 49th International Symposium on Microarchitecture (MICRO), Taipei, Taiwan, October 2016.
  7. S. Fan, T. Salonidis, B.C. Lee. "A framework for collaborative sensing and processing of mobile data streams," Proc. International Conference on Mobile Computing and Networking (MobiCom), New York, NY, October 2016.
  8. S. Fan. "Towards energy-efficient mobile sensing: Architectures and frameworks for heterogeneous sensing and computing," Ph.D. Dissertation, Duke University, September 2016.
  9. Z. Huang, A.D. Hilton, B.C. Lee. "Decoupling loads for nano-instruction set computers," Proc. 43rd International Symposium on Computer Architecture (ISCA), Seoul, Korea, June 2016.
  10. S. Fan*, S.M. Zahedi*, B.C. Lee. "The computational sprinting game," Proc. 21st International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS). Atlanta, GA, April 2016. *Co-First Authors. Best Paper Award.
  11. S. Fan, B.C. Lee. "Evaluating asymmetric multiprocessing for mobile applications," Proc. International Symposium on Performance Analysis of Systems and Software (ISPASS). Uppsala, Sweden, April 2016.
  12. B.C. Lee "Datacenter design and management: A computer architect's perspective," Synthesis Lectures on Computer Architecture, 11(1):1-121, February 2016.


  13. B.C. Lee. "Applied statistical inference for system design and management," Proc. 33rd IEEE International Conference on Computer Design (ICCD). New York, NY, October 2015.
  14. Q. Wang, B.C. Lee. "Modeling communication costs in blade servers," Proc. 8th Workshop on Power-Aware Computing and Systems (HotPower). Monterey, CA, October 2015.
  15. W. Feng, B.C. Lee, K. Agrawal, R. Bodik, L. Ceze, L. Tang. "Exploiting Parallelism and Scalability," Report on an NSF-Sponsored Workshop. Arlington, VA, June 2015.
  16. S.M. Zahedi, B.C. Lee. "Sharing incentives and fair division for multiprocessors," IEEE Micro, Top Picks from Computer Architecture Conferences, 35(3):92-100, May/June 2015.


  17. M. Guevara. "Coordinating the design and management of heterogeneous datacenter resources," Ph.D. Dissertation, Duke University, May 2014.
  18. S.M. Zahedi, B.C. Lee. "REF: Resource elasticity fairness with sharing incentives for multiprocessors," Proc. 19th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS). Salt Lake City, UT, March 2014.
  19. M. Guevara, B. Lubin, B.C. Lee. "Strategies for anticipating risk in heterogeneous system design," Proc. 20th IEEE International Symposium on High-Performance Computer Architecture (HPCA). Orlando, FL, February 2014.
  20. M. Guevara, B. Lubin, B.C. Lee. "Market mechanisms for managing datacenters with heterogeneous microarchitectures," ACM Transactions on Computer Systems (TOCS), 32(1):3.1-3.31, February 2014.


  21. E. Bragg, M. Guevara, B.C. Lee. "Understanding query complexity and its implications for energy-efficient web search," Proc. International Symposium on Low Power Electronics and Design (ISLPED), Beijing, China, September 2013.
  22. S. Xi, M. Guevara, J. Nelson, P. Pensabene, B.C. Lee. "Understanding the critical path in power state transition latencies," Proc. International Symposium on Low Power Electronics and Design (ISLPED), Beijing, China, September 2013.
  23. M. Guevara, B. Lubin, B.C. Lee. "Navigating heterogeneous processors with market mechanisms," Proc. 19th IEEE International Symposium on High-Performance Computer Architecture (HPCA). Shenzhen, China, February 2013.
  24. T. Ham, B.K. Chelepalli, N. Xue, B.C. Lee. "Disintegrated control for power-efficient and heterogeneous memory systems," Proc. 19th IEEE International Symposium on High-Performance Computer Architecture (HPCA). Shenzhen, China, February 2013.


  25. K. Malladi, I. Shaeffer, L. Gopalakrishnan, D. Lo, B.C. Lee, M. Horowitz. "Rethinking DRAM power modes for energy proportionality," Proc. 45th IEEE/ACM International Symposium on Microarchitecture (MICRO). Vancouver, Canada, December 2012.
  26. W. Wu, B.C. Lee. "Inferred models for dynamic and sparse hardware-software spaces," Proc. 45th IEEE/ACM International Symposium on Microarchitecture (MICRO). Vancouver, Canada, December 2012.
  27. K. Malladi, F.A. Nothaft, K. Periyathambi, B.C. Lee, C. Kozyrakis, M. Horowitz. "Towards energy-proportional datacenter memory with mobile DRAM," Proc. 39th IEEE/ACM International Symposium on Computer Architecture (ISCA). Portland, OR, June 2012.


  28. R. Hameed, W. Qadeer, M. Wachs, O. Azizi, A. Solomatnikov, B.C. Lee, S. Richardson, C. Kozyrakis, M. Horowitz. "Understanding sources of inefficiency in general-purpose chips," Communications of the ACM (CACM), Research Highlight, 54(10):85-93, October 2011.
  29. V.J. Reddi, B.C. Lee, T. Chilimbi, K. Vaid. "Mobile processors for energy-efficient web search," ACM Transactions on Computer Systems (TOCS), 29(4):9.1-9.39, August 2011.


  30. O. Shacham, O. Azizi, M. Wachs, W. Qadeer, Z. Asgar, K. Kelley, J.P. Stevenson, A. Solomatnikov, A. Firoozshahian, B.C. Lee, S. Richardson, M. Horowitz. "Rethinking digital design: Why design must change," IEEE Micro, 30(6):9-24, November/December 2010.
  31. B.C. Lee, D. Brooks. "Applied inference: Case studies in microarchitectural design," ACM Transactions on Architectecture and Code Optimization (TACO), 7(2):8.1-8.37, September 2010.
  32. B.C. Lee, E. Ipek, O. Mutlu, D. Burger. "Phase change memory architecture and the quest for scalability," Communications of the ACM (CACM), Research Highlight, 53(7):99-106, July 2010.
  33. O. Azizi, A. Mahesri, B.C. Lee, S. J. Patel, M. Horowitz. "Energy performance tradeoffs in processor architecture and circuit design: A marginal cost analysis," Proc. 37th IEEE/ACM International Symposium on Computer Architecture (ISCA). Saint-Malo, France, June 2010.
  34. R. Hameed, W. Qadeer, M. Wachs, O. Azizi, A. Solomatnikov, B.C. Lee, S. Richardson, C. Kozyrakis, M. Horowitz. "Understanding sources of inefficiency in general-purpose chips," Proc. 37th IEEE/ACM International Symposium on Computer Architecture (ISCA). Saint-Malo, France, June 2010.
  35. V.J. Reddi, B.C. Lee, T. Chilimbi, K. Vaid. "Web search using mobile cores: Quantifying and mitigating the price of efficiency," Proc. 37th IEEE/ACM International Symposium on Computer Architecture (ISCA). Saint-Malo, France, June 2010. Also Microsoft Research MSR-TR-2009-105.
  36. B.C. Lee, P. Zhou, J. Yang, Y. Zhang, B. Zhao, E. Ipek, O. Mutlu, D. Burger. "Phase change technology and the future of main memory," IEEE Micro Top Picks from Computer Architecture Conferences, 30(1):131-141, January/February 2010.


  37. J. Condit, E.B. Nightingale, C. Frost, E. Ipek, B.C. Lee, D. Burger, D. Coetzee. "Better I/O through byte-addressable, persistent memory," Proc. 22nd ACM Symposium on Operating System Principles (SOSP). Big Sky, MT, October 2009.
  38. X. Liang, B.C. Lee, G.-Y. Wei, D. Brooks. "Design and test strategies for microarchitectural post-fabrication tuning," Proc. 27th IEEE International Conference on Computer Design (ICCD). Lake Tahoe, CA, October 2009. Also Harvard TR-06-08.
  39. K. Lovin, B.C. Lee, X. Liang, D. Brooks, G.-Y. Wei. "Empirical performance models for 3T1D memories," Proc. 27th IEEE International Conference on Computer Design (ICCD). Lake Tahoe, CA, October 2009. Also Harvard TR-03-08.
  40. B.C. Lee, E. Ipek, O. Mutlu, D. Burger. "Architecting phase change memory as a scalable DRAM alternative," Proc. 36th IEEE/ACM International Symposium on Computer Architecture (ISCA). Austin, TX, June 2009. IEEE Top Picks, ACM Research Highlight.


  41. B.C. Lee, J. Collins, H. Wang, D. Brooks. "CPR: Composable performance regression for scalable multiprocessor models," Proc. 41st IEEE/ACM International Symposium on Microarchitecture (MICRO). Lake Como, Italy, November 2008. Best Paper Nomination.
  42. B. C. Lee. "Statistical inference for efficient microarchitectural analysis," Ph.D. Dissertation, Harvard University, May 2008.
    (ACM Doctoral Dissertation Award Nomination)
  43. B.C. Lee. "Corporate social responsibility and the globalization of 'local values'," 38th St. Gallen Symposium: Global Capitalism - Local Values . St. Gallen, Switzerland, May 2008.
  44. B.C. Lee, D. Brooks. "Efficiency trends and limits from comprehensive microarchitectural adaptivity," Proc. 13th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS). Seattle, WA, March 2008.
  45. B. C. Lee, D. Brooks. "Roughness of microarchitectural design topologies and its implications for optimization," Proc. 14th IEEE International Symposium on High Performance Computer Architecture (HPCA). Salt Lake City, UT, February 2008.


  46. B.C. Lee, D. Brooks. "A tutorial in spatial sampling and regression strategies for microarchitectural analysis," IEEE Micro Special Issue on Hot Tutorials, 27(3):74-93, May/June 2007.
  47. B.C. Lee. "Flattening the world efficiently: Digital sustainability for the twenty-first century," 37th St. Gallen Symposium: The Power of Natural Resources. St. Gallen, Switzerland, May 2007.
  48. B.C. Lee, D. Brooks, B. de Supinski, M. Schulz, K. Singh, S. McKee. "Methods of inference and learning for performance modeling of parallel applications," Proc. 12th ACM Symposium on Principles and Practice of Parallel Programming (PPoPP). San Jose, CA, March 2007.
  49. B.C. Lee, D. Brooks. "Illustrative design space studies with microarchitectural regression models," Proc. 13th IEEE International Symposium on High-Performance Computer Architecture (HPCA). Phoenix, AZ, February 2007.


  50. B.C. Lee, D. Brooks. "Accurate and efficient regression modeling for microarchitectural performance and power prediction," Proc. 12th ACM International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS). San Jose, CA, October 2006. Also Harvard TR-08-06.
  51. B. C. Lee, D. Brooks. "Statistically rigorous regression modeling for the microprocessor design space," Proc. Workshop on Modeling, Benchmarking, and Simulation (MoBS) in conjunction with ISCA-33. Boston, MA, June 2006.
  52. Y. Li, B. C. Lee, D. Brooks, Z. Hu, K. Skadron. "Impact of thermal constraints on multi-core architectures," Proc. 10th Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronics Systems (ITHERM). Orlando, FL, May 2006.
  53. Y. Li, B. C. Lee, D. Brooks, Z. Hu, K. Skadron. "CMP design space exploration subject to physical constraints," Proc. 12th IEEE International Symposium on High-Performance Computer Architecture (HPCA). Austin, TX, February 2006.


  54. B. C. Lee, D. Brooks. "Effects of pipeline complexity on SMT/CMP power-performance efficiency," Proc. Workshop on Complexity Effective Design (WCED) in conjunction with ISCA-32. Madison, WI, June 2005.


  55. B. C. Lee, R. Vuduc, J. Demmel, K. Yelick. "Performance models for evaluation and automatic tuning of symmetric sparse matrix-vector multiply," Proc. 33rd International Conference on Parallel Processing (ICPP). Montreal, Canada, August 2004. (Best Paper)


  56. R. Vuduc, J. Demmel, K. Yelick, S. Kamil, R. Nishtala, B. C. Lee. "Performance optimizations and bounds for sparse matrix-vector multiply," Proc. IEEE/ACM International Conference for High Performance Computing, Networking, Storage and Analysis (SC). Baltimore, MD, November 2002. (Best Student Paper Finalist)



Technical Reports

  1. B. C. Lee, M. Horowitz. "Integrated inference for hardware-software efficiency: A case study in SpMV and Smart Memories," Technical Report No. TR-10-01, Systems Architecture Integration Laboratory, Duke University, August 2010.
  2. Y. Li, K. Skadron, B. C. Lee, D. Brooks. "Quantifying latency and throughput compromises in CMP designs," Technical Report CS-2006-26, Department of Computer Science, University of Virginia, December 2006.
  3. B. C. Lee, M. Schulz, B. de Supinski. "Regression strategies for parameter space exploration: A case study in semicoarsening multigrid and R," Technical Report UCRL-TR-224851, Lawrence Livermore National Laboratory, September 2006.
  4. B. C. Lee, "An architectural assessment of SPEC CPU benchmark relevance," Technical Report TR-02-06, Harvard University, January 2006.
  5. H. Gahvari, O. Kamil, B. Lee, M. Ngo, A. Solar. "A survey of performance optimizations for Titanium immersed boundary simulation," Project Report, Computer Science 267, University of California, Berkeley, Spring 2004.
  6. B. C. Lee, R. Vuduc, J. Demmel, K. Yelick, M. de Lorimier, L. Zhong. "Performance optimizations and bounds for sparse symmetric matrix-multiple vector multiply," Technical Report UCB/CSD-03-1297, University of California, Berkeley, November 2003.



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