// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/03/a/RAM64.hdl

/**
 * Memory of 64 registers, each 16 bit-wide. Out hold the value
 * stored at the memory location specified by address. If load=1, then 
 * the in value is loaded into the memory location specified by address 
 * (the loaded value will be emitted to out after the next time step.)
 */

CHIP RAM64 {
    IN in[16], load, address[6];
    OUT out[16];

    PARTS:

DMux8Way(in=load,sel=address[3..5],a=a,b=b,c=c,d=d,e=e,f=f,g=g,h=h);

RAM8(in=in,load=a,address=address[0..2],out=oa);
RAM8(in=in,load=b,address=address[0..2],out=ob);
RAM8(in=in,load=c,address=address[0..2],out=oc);
RAM8(in=in,load=d,address=address[0..2],out=od);
RAM8(in=in,load=e,address=address[0..2],out=oe);
RAM8(in=in,load=f,address=address[0..2],out=of);
RAM8(in=in,load=g,address=address[0..2],out=og);
RAM8(in=in,load=h,address=address[0..2],out=oh);

Mux8Way16(a=oa,b=ob,c=oc,d=od,e=oe,f=of,g=og,h=oh,sel=address[3..5],out=out);

}