Overview

Lecture location: Fitzpatrick Schiciano B (CIEMAS 1466)
Lecture time: Tue/Thu 10:05am - 11:20am

Instructor: Dr. Tyler Bletsch
Email: Tyler.Bletsch AT duke.edu
Office Hours:

• After every lecture: In classroom.
  ^ These are *real* office hours, not just answering a few short questions - feel free to approach after class with substantive issues.
• By appointment: Feel free to email to meet if the above times don't work for you.

Teaching Assistants:

• TBA

TA Office Hours: TBA

Recitations:

Section(s)	Room	Time	Lead(s)
441/442	Teer 210/216	Thu 1:25pm-4:25pm	TBA
521/522	Teer 210/216	Fri 10:05am-1:05pm	TBA

Note: The sections listed together may be effectively merged in practice.

Links:

• Canvas - submit code and see grades
• Ed forum - get help and discuss course material
• GradeScope - submit homework assignments and get feedback
• Feedback form - send anonymous feedback to the instructor

Schedule

#	Date	Lecture	Lab Wed/Thu/Fri	Homework due (11:59:00pm)
1	Tue 8/26	Intro, booleans, and logic
2	Thu 8/28	Intro, booleans, and logic	Lab 1: Intro to Verilog
	Tue 9/2	Intro, booleans, and logic		(Wed 9/3) Homework 1
3	Thu 9/4	Addition/subtraction	Lab 2: Ripple Carry Adder
4	Tue 9/9	Addition/subtraction	Heads up: Do Lab 3's pre-lab tasks before you get there!	(Wed 9/10) Homework 2
5	Thu 9/11	Intro to CAD	Lab 3: Comparator
6	Tue 9/16	Latches and registers		(Wed 9/17) Homework 3
7	Thu 9/18	Multiplication	Lab 4: Instrumentation - Instrumentation intro	(Fri 9/19) CP1: ALU
8	Tue 9/23	Multiplication	Heads up: All outstanding lab tasks must be done before next week!	(Wed 9/24) Homework 4
9	Thu 9/25	Division	(CP help)	(Fri 9/26) CP2: Regfile
10	Tue 9/30	Memory elements
11	Thu 10/2	Logic minimization	Lab 5: Memory Elements - Gate delay demo	(Fri 10/3) CP3 milestone 1: Proof of life
12	Tue 10/7	Midterm 1 - Practice midterm
13	Thu 10/9	Logic minimization	Lab 6: VGA & Lab 7: Keyboard/ADC - Multivoltage circuit video	(Thu 10/9) CP3 milestone 2: Mul
	Tue 10/14	FALL BREAK
14	Thu 10/16	Pipelined processors	Lab 6: VGA & Lab 7: Keyboard/ADC - Multivoltage circuit video
15	Tue 10/21	Finite state machines		(Tue 10/21) CP3: Mul/div
16	Thu 10/23	Finite state machines	Lab 8: Audio and PWM	(Thu 10/23) Homework 5
17	Tue 10/28	Making stuff - Chris Bingham: Design Resources		(Mon 10/27) CP4 milestone 1: Baby CPU
18	Thu 10/30	NMOS, PMOS, and CMOS	Lab 9: FSM	(Sun 11/2) CP4 milestone 2: Hazardous CPU
19	Tue 11/4	NMOS, PMOS, and CMOS	Heads up: All outstanding lab tasks must be done before next week!	(Wed 11/5) Project proposal
20	Thu 11/6	Error correcting codes	(Project help)
21	Tue 11/11	Digital testing		(Tue 11/11) CP4: Complete CPU
22	Thu 11/13	PLDs and FPGAs	(Project help)	(Fri 11/14) CP4: Optional technical report
23	Tue 11/18	Chill chat		(Wed 11/19) Homework 6
24	Thu 11/20	Midterm 2 - Practice midterm	(Project help)
25	Tue 11/25	Chill chat
	Thu 11/27	THANKSGIVING BREAK	THANKSGIVING BREAK
26	Tue 12/2	Chill chat
27	Thu 12/4	Chill chat	Demo time	(Fri 12/5, 10am) Project demos begin (Wed 12/10, 5pm) Project demos end (Wed 12/10) Project materials due: Report (GradeScope) Code (Canvas) Team eval (GradeScope)

Additional resources

Lecture videos:

• Lecture recordings from 2024 Fall
• Lecture recordings from 2023 Fall

Setup guides:

• Tool Chain Setup
• How to Disable GitHub Copilot for Verilog
• Testing Verilog Modules
  • Making test benches (supplementary video)
• Hardware Design Setup
• Validating Timing in Vivado
  • Circuit timing in Vivado (supplementary video)
  • Wrapper files
  • Using a PLL to make a custom clock in Vivado (supplementary video)
• Git Setup for ECE 350

Provided code:

• multdiv-simulator: A Python simulator of the multiplication and division algorithms used in this course

Supplemental reading:

• John Board's version of the slides from Spring 2024 (all topics in one giant doc)
• John Board's version of the slides from Spring 2023 (all topics in one giant doc)
• Wallace Tree resources:
  • Implementation of a CMOS Wallace-tree Multiplier by Li et al.
  • MIT courseware, 6.111: Multiplication
  • The textbook that's available in the lab (starting around pg. 265)

Datasheets:

• Nexys A7: Details about the FPGA used throughout this course
• 2-Input NAND Gate: Details about the 74LS00 IC Chip used in Lab 2
• 8-Input Multiplexer: Details about the 74LS151 TTL IC Chip used in Lab 3
• 2-Input NOR Gate: Details about the 74LS02 IC Chip used in Lab 4
• JK Flip Flop: Details about the 74LS109 IC Chip used in Lab 4
• Precision Timer: Details about the NE555 Timer used in Lab 4
• TXS0108E level shifter demoed in the multivoltage circuit video for Lab 7
• ADC0808 analog-to-digital converter demoed in the multivoltage circuit video for Lab 7

Syllabus & policies

Course synopsis

Design and implementation of combinational and sequential digital systems with special attention to digital computers. The use of computer-aided design tools, hardware description languages, and programmable logic chips to facilitate larger and higher performance designs will be stressed. Laboratory exercises and group design projects will reinforce the various design techniques discussed in class.

Includes homeworks, labs, and a multi-checkpoint project in which you'll develop a full CPU and deploy it in support of a real-world task.

Pre-requisite: ECE/CS 250D

Grading breakdown

Note: Subject to change.

Category	%
Homeworks	15%
Midterm exams	20%
Processor + Checkpoints	45%
Final project	20%

No final exam!

Lab completion requirement: There is no explicit grades for labs, but you must do all the lab tasks (in or out of lab) and show your TA to be able to pass the class.

Assignment policies

You are expected to complete the homework and checkpoints individually unless otherwise stated. However, you may discuss topics covered in the class.

Late homework submissions incur penalties as follows:

• Submission is 0-24 hours late: total score is multiplied by 0.9
• Submission is 24-48 hours late: total score is multiplied by 0.8
• Submission is more than 48 hours late: no credit

Late checkpoint submissions incur penalties as follows:

• No credit without prior permission from the instructor

NOTE: If you feel in advance that you may need an extension, contact the instructor. We can work with you if you see a scheduling problem coming, but extensions cannot be granted at or near the due date!

Your grade will be based on what and when you submit to GradeScope.

Grade appeals

All regrade requests must be in writing. Email the TA with your questions. After speaking with the TA, if you still have concerns, contact the instructor.

All regrade requests must be submitted to the instructor no later than 1 week after the assignment was returned to you.

Academic integrity

I take academic integrity extremely seriously. Academic misconduct will not be tolerated, and all suspected violations of the Duke Honor Code will be referred to the Office of Student Conduct (for undergraduates) or the departmental Director of Graduate Studies (for graduate students). A student found responsible for academic dishonesty faces formal disciplinary action, which may include suspension. A student twice suspended automatically faces a minimum 5-year separation from Duke University.

In addition to the measures taken by the university, the affected assignment(s) will receive zero credit, or possibly -100% in egregious cases.

If you are considering this course of action, please see me instead, and we can work something out! I want every student in my course to be successful.